1. Field of the Invention
The present invention generally relates to electrostatic discharge (ESD), and more particularly to a simulation method for an ESD circuit layout.
2. Description of Related Art
Electrostatic discharge (ESD) is harmful to integrated circuits made of semiconductor materials such as silicon and silicon oxide, which may be permanently damaged by a sudden and brief current or voltage. Accordingly, integrated circuits are commonly equipped with ESD protection circuits and need to be subjected to various ESD tests during their designing and manufacturing processes for verifying their resistance level or insusceptibility to ESD. The human-body model (HBM) is one commonly used test model for characterizing ESD that imitates a human's touch on an integrated circuit, and machine model (MM) is another one that imitates a machine's contact with the integrated circuit.
As those in the field well know, it is most advantageous and affordable to have defective ESD circuits uncovered as early as possible during the designing and manufacturing process. Unfortunately, most test schemes fail to opportunely identify defective ESD circuits as even they can pass the circuit functionality test.
As a result, defective ESD circuits usually cannot be successfully detected until the manufactured (i.e., physical) integrated circuits burn out while being subjected to ESD testing. At that time, the photomask used for manufacturing the integrated circuits is discarded, the circuit layout is modified, a new photomask is prepared and used to manufacture the integrated circuits again, and the newly manufactured integrated circuits are once again subjected to ESD testing. The procedure mentioned above will need to be iterated again and again until the integrated circuits eventually pass the ESD test.
For the foregoing reasons, a need has arisen to propose a novel method for simulating an ESD circuit layout in an effective, economic and expedient manner.